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HomeElectronicsBrute drive mitigation of PWM Vdd and floor “saturation” errors

Brute drive mitigation of PWM Vdd and floor “saturation” errors



Brute drive mitigation of PWM Vdd and floor “saturation” errors

An excerpt from Christopher Paul’s “Parsing PWM (DAC) efficiency: Half 1—Mitigating errors”:

 “I used to be shocked to find that when an output of a preferred µP I’ve been utilizing is configured to be a continuing logic low or excessive and is loaded solely by a ten MΩ-input digital multimeter, the voltage ranges are in some circumstances greater than 100 mV from provide voltage VDD and floor…Let’s name this saturation errors.”

Wow the engineering world along with your distinctive design: Design Concepts Submission Information

The accuracy of PWM DACs depends upon a number of components, however none is extra vital than their analog switching components’ capacity to reliably and exactly output zero and reference voltage ranges in response to the corresponding digital states. Typically nevertheless, as Christopher Paul observes within the cited design concept (Half 1 of a 4-part collection), they don’t. The mechanism behind these deviations isn’t totally clear, but when they might be reliably eradicated, the impression on PWM efficiency must be constructive. Determine 1 suggests a (actually) brute-force repair.

Determine 1 U1 is a multi-pole (e.g., 74AC04 hex inverter) PMW swap the place op-amp A1 forces swap zero state to precisely monitor 0 = zero volts, op-amp A2 does the job for 1 = Vdd.

U1 pin 5’s connection to pin 14 drives pin 6 to logic 0, sensed by A1 pin 6. A1 pin 7’s connection to U1 pin 7 forces the pin 6 voltage to precisely zero volts, and thereby forces any U1 output to the identical correct zero stage when the related swap is at logic 0.

Equally, U1 pin 13’s connection to pin 7 drives pin 12 to logic 1, sensed by A2 pin 2. A2 pin 1’s connection to U1 pin 14 forces the pin 12 voltage to precisely Vdd, and thereby forces any U1 output to the identical correct Vref stage when the related swap is at logic 1.

Thus, any extant “saturation errors” are compelled to zero, whatever the particulars of the place they’re really coming from.

Vdd will sometimes be c.a. 5.00V. And V+ and V- can come from a single 5-V provide through any of quite a lot of discrete or monolithic rail enhance circuits. Determine 2 is one sensible chance.

Determine 2 A sensible supply for V+ and V- set R1 and R2 = 200k for ∆ = 1volt.

The Determine 2 circuit was initially described in “Environment friendly digitally regulated bipolar voltage rail booster”.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.

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