Intel’s embedded multi-die interconnect bridge (EMIB) expertise—aiming to handle the rising complexity in heterogeneously built-in multi-chip and multi-chip (let) architectures—made waves at this yr’s Design Automation Convention (DAC) in San Francisco, California. It delivers superior built-in IC packaging options that embody planning, prototyping, and signoff throughout a broad vary of integration applied sciences corresponding to 2.5D and 3D IC.
At DAC, Intel exhibited tie-ups with key EDA and IP companions to make sure that their heterogenous design instruments, flows and methodologies, and reusable IP blocks are totally enabled and certified to assist EMIB meeting expertise.
Determine 1 A silicon bridge is embedded inside a bundle to attach a number of dies. Supply: Intel
On the coronary heart of those initiatives was Intel Foundry’s Bundle Meeting Design Equipment (PADK), which permits engineers to create EMIB-based bundle designs. Intel’s PADK—comprising a design information, guidelines, and stack-up that allow chip designers to finish and confirm an EMIB design effectively—goals to handle chip design complexity and facilitate EDA instrument enablement.
PADK permits reference flows that assist instruments from all main EDA distributors to facilitate a PADK-driven meeting verification. Beneath is a sneak peek at Intel’s Foundry’s current collaborations with main EDA distributors for EMIB enablement.
Collaboration with EDA trio
- Simens EDA
At DAC 2024, Siemens EDA introduced instrument certifications for EMIB enablement for designing extremely complicated ICs and superior packaging. The certifications embody Solido SPICE—a part of the Solido Simulation Suite software program—for the foundry’s Intel 16 and Intel 18A course of nodes.
Earlier, in February 2024, Siemens EDA introduced the supply of the EMIB reference move to permit design engineers perform early bundle meeting prototyping, hierarchical system floorplanning, co-design optimization, and verification of the whole detailed implementation. The reference move, constructed round Intel Foundry’s PADK, permits engineers to deal with the complete vary of essential duties wanted for a profitable design and tape-out.
Determine 2 The EMIB reference move permits design engineers to create high-density interconnect for heterogeneous chips. Supply: Siemens EDA
- Synopsys
Synopsys additionally exhibited a multi-die reference move for Intel Foundry on the DAC 2024 ground. Powered by Synopsys.ai EDA suite, it goals to offer designers with a complete and scalable resolution for quick heterogeneous integration utilizing EMIB meeting expertise.
The reference move, enabled by Synopsys 3DIC Compiler, supplies a unified co-design and evaluation resolution to speed up the event of multi-die designs in any respect levels from silicon to methods. Furthermore, Synopsys 3DSO.ai, which is natively built-in with Synopsys 3DIC Compiler, permits optimization for sign, energy, and thermal integrity.
Ansys, a provider of electrothermal instruments at the moment within the means of being acquired by Synopsys, can be offering multi-physics signoff options for Intel’s 2.5D chip meeting expertise, which makes use of EMIB expertise to attach the die flexibly and with out the necessity for through-silicon vias (TSVs). Its RedHawk-SC Electrothermal EDA platform permits multi-physics evaluation of two.5D and 3D ICs with a number of dies.
- Cadence Design Techniques
Cadence, one other member of EDA trio, has additionally joined palms with Intel Foundry to certify an built-in superior packaging move using EMIB expertise to handle the rising complexity in heterogeneously built-in multi-chip(let) architectures. This EMIB move permits design groups to seamlessly transition from early-stage system-level planning, optimization and evaluation to DRC-aware implementation, and bodily signoff with out changing knowledge between completely different codecs.
EDA instrument enablement
Intel, which has led the packaging expertise improvement curve for a few a long time, has now launched two superior packaging applied sciences to scale silicon space by connecting a number of dies in a single bundle. Whereas EMIB connects a number of chips facet by facet in a bundle, chips are stacked on prime of each other in a 3D trend in Foveros.
Rahul Goyal, VP and GM for product and design ecosystem enablement at Intel, says EMIB expertise embodies a differentiated method to multi-die meeting in comparison with conventional stacking methods. Intel has already carried out EMIB expertise in its personal chips, together with GPU Max Collection (code-named Ponte Vecchio), 4th Gen Intel Xeon and Xeon 6 processors, and Intel Stratix 10 FPGAs.
Determine 3 Intel Foundry developed EMIB to attach a number of dies in a single bundle. Supply: Intel
Nevertheless, EMIB, like different superior packaging applied sciences, presents new challenges associated to the design and packaging complexities of multi-die architectures. So, incorporating a wide range of EDA instruments into Intel’s PADK is an effective begin. It’ll assist chip designers implement and confirm EMIB designs successfully and effectively.
Associated Content material
- A thermal-aware IC design methodology
- The Significance of 3D IC Ecosystem Collaboration
- Reliability challenges in 3D IC semiconductor design
- How the Worlds of Chiplets and Packaging Intertwine
- Heterogeneous Integration and the Evolution of IC Packaging
googletag.cmd.push(operate() { googletag.show(‘div-gpt-ad-native’); });
–>
The publish Intel bolsters EMIB packaging with EDA instruments enablement appeared first on EDN.
