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HomeElectronicsVoltage inverter design thought transmogrifies right into a 1MHz VFC

Voltage inverter design thought transmogrifies right into a 1MHz VFC



Voltage inverter design thought transmogrifies right into a 1MHz VFC

It’s attention-grabbing, helpful, and enjoyable that fundamental digital topologies typically end up to have utility in a number of and surprisingly completely different functions. Determine 1 reveals an instance of such a circuit. It’s a cost pump voltage inverter circuit initially printed in A easy, correct, and environment friendly cost pump voltage inverter for $1.

Determine 1 Primary voltage inverter circuit scaled for effectivity at 100 kHz and several other milliamps of present output.

Configured thusly for the voltage inverter utility, the pump is straightforward and low-cost. It attracts solely about 1µA per kHz (unloaded) from the 5-V rail. 

Wow the engineering world along with your distinctive design: Design Concepts Submission Information

An attention-grabbing variation outcomes if pump capacitor C2 is diminished by a number of orders of magnitude. This makes the present pumped immediately proportional to oscillator frequency: Ipump = 5*C2*Fpump

Ranging from that concept, then including some easy discrete parts, our unique inverter circuit turns into the core of a reasonable, quick (1 MHz), low energy voltage to frequency converter. Determine 2 reveals how.

Determine 2 Modified voltage inverter turns into energy thrifty 1MHz VFC.

Enter present = Vin/R1 expenses C3 which causes transconductance amplifier Q1,Q2 to sink, rising present from Schmidt set off oscillator cap C1. This will increase U1c oscillator frequency and the present pumped by U1a,b and C2. It’s because the pump present has unfavorable polarity (keep in mind we began with a voltage inverter circuit); it completes a suggestions loop that constantly balances pump present to equal enter present:

Ipump = 5*C2*Fpump = Vin/R1

Fpump = Vin/(5*C2*R1) = Vin/(5*100pF*10,000) = 200kHz*Vin

Q3 offers the ramp reset pulse that initiates every oscillator cycle. R6 limits C2 discharge present to stop driving U1 pin 1 substrate diodes into conduction, which may steal a fraction of Ipump and thus create nonlinearity. The ratio of R5/R3 is chosen to stability Q2/Q1 collector currents at Vin and Fpump equal zero, thus minimizing Vin zero offset. Consequently, linearity and nil offset errors are lower than 1% of full-scale.

Nevertheless, this leaves open the opportunity of unacceptable scale issue error if the +5-logic energy rail isn’t correct sufficient. 

What if we would like a precision voltage reference that’s unbiased of +5 instability? Determine 3 solutions that query.

Determine 3 U2 shunt reference stabilizes C2 cost to a +5 unbiased precision 2.50 V.

Including the reference does, nonetheless, improve elements price by about half a buck and max energy consumption by about half a milliamp. These totals are nonetheless relatively cheap costs to pay for correct and quick conversions. Sure, for a VFC, 10-bit decision in a millisecond is fairly quick.

Observe that R1 could be chosen to implement nearly any desired Vin full-scale issue.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.

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